Chip architecture is moving beyond the traditional uniplanar arrangement of chips, i.e., where chips are positioned in a single plane. Three-dimensional (“3D”) architectures are becoming more common and offer many advantages over uniplanar architectures. 3D architectures or 3D chip stacks, as used herein, encompass architectures where chips are positioned on more than one plane and may be integrated both horizontally and vertically into a single circuit. Additionally, 3D architectures also encompass the situation where there exists more than one vertical stack of chips in the circuit. 3D architectures present a variety of challenges for calibrating the chips in the circuit. Connections between chips in a 3D architecture typically involve routing connections through a silicon interposer and at least one Through Silicon Via (“TSV”). Additionally, the chips in a 3D architecture may be of different varieties, such as, but not limited to, processors, memory (of various types and capacities), digital signal processors (“DSP”), radio frequency (“RF”) modules, etc., as would be familiar to those of skill in the art.
One of the challenges of a 3D architecture is that certain chips may be more difficult to connect to for standard calibration or testing. Furthermore, the different varieties of chips may cause an unbalanced load between any two given chip sets in the 3D architecture. Thus, an optimal driving strength between a first set of two given chips may not be the same as the optimal driving strength between a second set of chips due to the difference in chip-to-chip loading. Additionally, there may be a range of operating speeds which need to be accounted for.
Traditional calibration methods for uniplanar architectures use a direct current (“DC”) method along with optimization methodologies such as board routing to minimize load unbalances to meet specified maximum operating speeds. This results in a fixed driving strength for all chips for all operating regimes. However, in a 3D architecture, for example, routing and loading are dependent upon the permutation of chips in the 3D architecture. Thus, if the traditional calibration methods are used in a 3D architecture, serious penalties may accrue such as a power penalty during times when the operating speed is less than the specified maximum as well as degraded signal integrity and/or a simultaneous switching output (“SSO”) problem due to a minimal time for peak current.